View AT91SAM7A20407_4220845.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* ARM7TDMI(R) ARM(R) Thumb(R) Processor Core
- High Performance 32-bit RISC - High-density 16-bit Instruction set (Thumb) - Leader in MIPS/Watt - Embedded ICE (In Circuit Emulation) 16 Kbytes Internal SRAM Fully Programmable External Bus Interface (EBI) - Maximum External Address Space of 6 Mbytes, Up to Four Chip Select Lines 8-level Priority, Vectored Interrupt Controller - Three External Interrupts Including One Fast Interrupt Line Ten Channel Peripheral Data Controller (PDC) 57 Programmable I/O Lines Four 16-bit General Purpose Timers (GPT) - Three Configurable Modes: Counter, PWM, Capture - Four External Clock Inputs, Three Multi-purpose I/O Pins per Timer Four 16-bit Simple Timers (ST) Four Channel 16-bit Pulse Width Modulation (PWM) Four CAN Controllers 2.0A and 2.0B Full CAN - One with 32 Buffers, Three with 16 Buffers Two USARTs - Support for J1587 and LIN Protocols One Master/Slave SPI Interface - 8 to 16-bit Programmable Data Length - Four External Serial Peripheral Chip Selects Two 8-channel 10-bit Analog to Digital Converters (ADC) Two 16-bit Capture Modules (CAPT) Programmable Watch Timer (WT) Programmable Watchdog (WD) Power Management Controller (PMC) - 32 kHz Oscillator, Main Oscillator and PLL IEEE 1149.1 JTAG Boundary-scan on all Digital Pins Fully Static Operation: 0 Hz to 30 MHz at VDDCORE=3.3V, 85C 3.0V to 5.5V Operating Voltage Range 3.0V to 3.6V Core, Memory and Analog Voltage Range -40 to +85C Operating Temperature Range Available in a 176-lead LQFP Package
* * * * * * * * * * * * * * * * * * * * * *
AT91 ARM(R) Thumb(R)- based Microcontrollers AT91SAM7A2
Summary
Description
The AT91SAM7A2 is based on the ARM7TDMI embedded processor. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91SAM7A2 has a direct connection to off-chip memory, including Flash, through the fully programmable External Bus Interface. An 8-level priority vectored Interrupt Controller in conjunction with the Peripheral Data Controller significantly improves the real time performance of the device. The device is manufactured using high-density CMOS technology. By combining the ARM7TDMI processor with an on-chip SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controllers, Timer Counter and Analog-to-Digital Converters, on a monolithic chip, the AT91SAM7A2 is a powerful device that provides a flexible, cost-effective solution to many compute-intensive embedded control applications in the automotive and industrial world.
6021BS-ATARM-06-Jul-04
PRELIMINARY
PRELIMINARY
Block Diagram
Figure 1. Block Diagram
5V VDDCORE SCANEN IRQ[1:0] 3V
VDDIO GND
I/O Power Supply
Core Power Supply Generic Interrupt Controller SPI
TEST
GND
TMS
TDO
TCK
FIQ
TDI
Select
JTAG
Advanced Memory Controller EBI
SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/MPIO NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO RXD0/MPIO TXD0/MPIO SCK0/MPIO RXD1/MPIO TXD1/MPIO SCK1/MPIO
Embedded ICE Arbiter ASB Controller SFM AMBATM Bridge ARM7TDMI Core
PIO 2 PDC Channels USART0 2 PDC Channels USART1 2 PDC Channels Timer T0 10 Channel PDC Controller
ADD[19:1] ADD0/NLB ADD20/CS3 NOE/NRD NWR0/NWE 3V NWR1/NUB NWAIT/UPIO NCS[2:0] D[15:0]
Internal SRAM 16 KB Reset NRESET 5V
PIO
PIO
Watch Dog CLK/UPIO RTCKI RTCKO MCKI MCKO
LFCLK Simple Timers Watch Timer CORECLK ST0 CH0 CH1
5V
T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO T0TCLK2/MPIO
Clock Controller with PLL
PIO TC0
PIO TC1 ST1 PIO TC2 CH0 CH1 Capture 0 PDC Channel Timer T1
PLLRC
3V
CAPT0
T1TIOA0/MPIO T1TIOB0/MPIO T1TCLK0/MPIO
Capture 1 PIO TC0 CAPT1 PDC Channel PWM
5V PWM0 PWM1 PWM2 PWM3
PIO[31:0]
UPIO 1 PDC Channel 1 PDC Channel CAN0 ADC0 ADC1 8-channel 8-channel 10-bit ADC 10-bit ADC Full Speed 16 Buffers CAN1 Full Speed 16 Buffers CAN2 CAN3
CH0 CH1 CH2 CH3
Analog Power Suppy
Full Speed Full Speed 32 Buffers 16 Buffers
CANRX3
VDDANA
CANRX0
CANTX0
CANRX1
CANTX1
CANRX2
ANA0IN[7:0]
Analog
ANA1IN[7:0]
5V
2
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
CANTX2
CANTX3
VREFP0
VREFP1
GND
AT91SAM7A2 - Summary
Pin Configuration
Table 1. Pinout
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name VDDIO IRQ0 IRQ1 FIQ SCK0/MPIO TXD0/MPIO RXD0/MPIO SCK1/MPIO TXD1/MPIO RXD1/MPIO VDDCORE CANTX3 CANRX3 CAPT0 CAPT1 SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/MPIO VDDIO GND NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO VDDIO GND T0TCLK2/MPIO T1TIOA0/MPIO T1TIOB0/MPIO T1TCLK0/MPIO NRESET UPIO0 UPIO1 UPIO2 UPIO3 UPIO4 Pin 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 Name GND VDDIO UPIO5 UPIO6 GND VDDIO UPIO7 UPIO 8 UPIO 9 UPIO 10 UPIO 11 UPIO 12 UPIO 13 UPIO 14 UPIO 15 UPIO 16 UPIO 17 UPIO 18 GND VDDIO UPIO19 UPIO20 UPIO21 UPIO22 UPIO23 UPIO24 UPIO25 UPIO26 UPIO27 UPIO28 UPIO29 UPIO30/NWAIT UPIO31/CORECLK CANTX0 CANRX0 CANTX1 CANRX1 CANTX2 CANRX2 PWM0 PWM1 PWM2 PWM3 GND Pin 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Name VDDIO VDDANA VREFP0 ANA0IN0 ANA0IN1 ANA0IN2 ANA0IN3 ANA0IN4 ANA0IN5 ANA0IN6 GND VDDANA ANA0IN7 VREFP1 ANA1IN0 ANA1IN1 ANA1IN2 ANA1IN3 ANA1IN4 ANA1IN5 ANA1IN6 ANA1IN7 GND VDDCORE RTCKI RTCKO GND VDDCORE SCANEN TEST TMS TDO TDI TCK GND PLLRC VDDCORE MCKI MCKO GND NWR1/NUB D8 D1 D0 Pin 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 55 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Name NOE/NRD NCS0 ADD1 D9 D2 VDDCORE D10 D3 D11 D4 D12 D5 D13 D6 D14 D7 D15 GND ADD0/NLB ADD17 ADD16 ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD20/CS3 VDDCORE NWR0/NWE NCS2 NCS1 ADD19 ADD18 ADD8 ADD7 ADD6 ADD2 ADD3 ADD4 ADD5 GND GND
PRELIMINARY
6021BS-ATARM-06-Jul-04
3
PRELIMINARY
Figure 2. Pin Configuration
176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
4
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
AT91SAM7A2 - Summary
Signal Description
Table 2. Signal Description
Module Name ADD[19:1] ADD0/NLB ADD20/CS3 D[15:0] EBI NOE NWR0/NWE NCS[2:0] NWR1/NUB NWAIT CORECLK IRQ[1:0] GIC FIQ Power-on Reset NRESET MCKI Master Clock MCKO PLLRC 32.768 kHz clock PIO RTCKI RTCKO UPIO[31:0] SCK0/MPIO USART0 RXD0/MPIO TXD0/MPIO SCK1/MPIO USART1 RXD1/MPIO TXD1/MPIO Capture0 Capture1 PWM CAPT0 CAPT1 PWM[3:0] Fast interrupt line Hardware reset input Master clock input Master clock output PLL RC network input 32.768 KHz clock input 32.768 KHz clock output General purpose I/O USART0 clock line USART0 receive line USART0 transmit line USART1 clock line USART1 receive line USART1 transmit line Capture input Capture input Pulse Width Modulation output I I I Connected to external crystal (4 to 6 Mhz) O I I O I/O I/O I/O I/O I/O I/O I/O I I O I/O I/O I/O (L) (Z) (Z) (Z) Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O (Z) (Z) (Z) (Z) (Z) (Z) (Z) Multiplexed with general purpose I/O Multiplexed with general purpose I/O Multiplexed with general purpose I/O Multiplexed with general purpose I/O Multiplexed with general purpose I/O Multiplexed with general purpose I/O Connected to external 32.768 Khz crystal L Schmitt input with internal filter Function External address bus External address line line/ Lower byte enable External address line/ Chip select External data bus Output enable Write enable Chip select lines Upper byte enable External Wait Core CLock External interrupt lines Type O O O I/O O O O O I O I Active Level Comments (Z)(1) L (Z) H (Z) (Z) L (Z) L (Z) L (Z) L (Z) L Disable at reset, multiplexed with UPIO30 Disable at reset, multiplexed with UPIO31
The EBI is tri-stated when NRESET is at a logical low level. Internal pull-downs on data bus bits
T0TIOA[2:0]/MPIO Capture/waveform I/O Timer T0 T0TIOB[2:0]/MPIO Trigger/waveform I/O T0TIOCLK[2:0]/MP External clock/trigger/input IO
PRELIMINARY
6021BS-ATARM-06-Jul-04
5
PRELIMINARY
Table 2. Signal Description (Continued)
Module Name T1TIOA/MPIO Timer T1 T1TIOB/MPIO T0TIOCLK/MPIO ANA0IN[7:0] ADC0 VREFP0 ANA1IN[7:0] ADC1 VREFP1 SPCK/MPIO MISO/MPIO SPI MOSI/MPIO NPCS[3:1]/MPIO Positive voltage reference SPI clock line SPI master in slave out SPI master out slave in SPI chip select I I/O I/O I/O I/O I/O I O I O I O I O I I O I I I H Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up Internal pull-down (connected GND or leave unconnected) 3.3V 3.3V 3.3V to 5V (Z) (Z) (Z) (Z) (Z) L L (H) L L (H) L L (H) L L (H) H Internal pull-down (connected GND or leave unconnected) Schmitt trigger, internal pull-up Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Positive voltage reference Analog input I I Function Capture/waveform I/O Trigger/waveform I/O External clock/trigger/input Analog input Type I/O I/O I/O I Active Level Comments (Z) (Z) (Z) Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O
NPCS0/NSS/MPIO SPI chip select (slave input) CANRX0 CAN0 CANTX0 CANRX1 CAN1 CANTX1 CANRX2 CAN2 CANTX2 CANRX3 CAN3 CANTX3 SCANEN TDI TDO JTAG TMS TCK TEST VDDCORE Power Supplies VDDANA VDDIO GND Note: Test Mode Select Test Clock Factory Test Core Power Supply Analog Power Supply I/O Lines Power Supply Ground CAN3 transmit line Scan enable Test Data In Test Data Out CAN2 transmit line CAN3 receive line CAN1 transmit line CAN2 receive line CAN0 transmit line CAN1 receive line CAN0 receive line
1. Values in brackets are the values at reset (H = High, L = Low, Z = High impedance state).
6
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
AT91SAM7A2 - Summary
Architectural Overview
The AT91SAM7A2 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for access to onchip peripherals and is optimized for low power consumption. The AMBATMBridge provides an interface between the ASB and the APB. The AT91SAM7A2 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 1 Mbytes of the 4 Gbyte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequently written registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit manipulation instructions. The ARM7TDMI processor operates in little-endian mode in the AT91SAM7A2 microcontroller. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI Datasheet.
AMC: Advanced Memory Controller
The AT91SAM7A2 embeds 16 Kbytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 27 MIPS @ 30 MHz by using the ARM(R) instruction set of the processor, minimizing system power consumption and improving on the performance of separate memory solutions. The EBI generates the signals which control the accesses to the external memories or peripheral devices. The EBI is fully programmable and can address up to 6 Mbytes. It has four chip selects and a 21-bit address bus, the upper bit of which is multiplexed with a chip select. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols allowing single clock cycle memory accesses. The main features are: * * * * * * * * External Memory Mapping Up to Four Chip Select Lines Byte Write or Byte Select Lines 8-bit or 16-bit Data Bus External Wait Remap of Boot Memory Two Different Read Protocols Programmable Wait State Generation
EBI: External Bus Interface
GIC: Generic Interrupt Controller
The AT91SAM7A2 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. The interrupt controller is connected to the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of the ARM7TDMITM processor. The processor's nFIQ line can only be asserted by the external fast interrupt request input: FIQ. The nIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ1. An 8-level priority encoder allows the customer to define the priority between the different nIRQ interrupt sources. Internal sources are programmed to
PRELIMINARY
6021BS-ATARM-06-Jul-04
7
PRELIMINARY
be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive.
PIO: Parallel I/O Controller
The AT91SAM7A2 has 57 configurable I/O lines. 32 pins (United PIO) on the AT91SAM7A2 are dedicated as general purpose I/O pins (UPIO0 to UPIO31). Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The United-PIO is controlled by a dedicated module. The others pins are configure in each module. An on-chip, 10-channel Peripheral Data Controller (PDC) transfers data between the on-chip peripherals and the on and off-chip memories without processor intervention. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and of the SPI. A single PDC channel is connected to each ADC and each Capture. Most importantly, the PDC removes the processor interrupt handling over-head and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64 Kbytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced.
PDC: Peripheral Data Controller
USART: Universal Synchronous Asynchronous Receiver Transmitter
The AT91SAM7A2 provides two identical, full-duplex, universal synchronous asynchronous receiver transmitter which are connected to the Peripheral Data Controller. The main features are: * * * * * * * * * * * Programmable Baud Rate Generator Parity, Framing and Overrun Error Detection Line Break Generation and Detection Automatic Echo, Local & Remote Loopback Modes Multi-drop Mode: Address Detection and Generation Interrupt Generation Two Dedicated Peripheral Data Controller Channels 5-, 6-, 7-, 8- and 9-bit Character Length Idle Flag for J1587 Protocol. Smart Card Transmission Error Feature Support LIN 1.2 Protocol with H/W Layer
SPI: Serial Peripheral Interface
The AT91SAM7A2 features an SPI that provides communication with external devices in master or slave mode. The SPI has four external chip selects that can be connected to up to 15 devices. The data length is programmable from 8- to 16-bit. As for the USART, a two-channel PDC is used to move data directly between memory and the SPI without CPU intervention for maximum real-time processing throughput.
CAN: Controller Area Network
The AT91SAM7A2 provides four CANs (2.0A and 2.0B). These are based upon serial communications protocol which efficiently supports distributed real-time control with a very high level of security (one with 32 mailboxes and the others with 16 mailboxes). The main features are: * * * * * Prioritization of Messages Multi-master System Wide Data Consistency Error Detection and Error Signaling Automatic Retransmission Of Corrupted Messages
8
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
AT91SAM7A2 - Summary
* * * * Automatic Reply After Receive a Remote Frame Time Stamp on Each Transfer Multicast Reception with Time Synchronization Continuous Reception Mode
GPT: General Purpose Timer
The AT91SAM7A2 features four General Purpose Timers. Each timer can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each General Purpose Timer has one external clock input, five internal clock inputs, and three multi-purpose input/output signals which can be configured by the user. Each timer drives an internal interrupt signal which can be programmed to generate processor interrupts via the AIC (Advanced Interrupt Controller). Three General Purpose Timers are grouped in the same block. This block has two global registers which act upon all three GPTs. The Block Control Register allows the three timers to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each timer, allowing them to be chained.
ST: Simple Timer
Simple Timers provide basic functions for timing calculation. Each channel of this timer has a specific prescalar and a 16-bit counter. The prescalar defines the clock frequency of the channel counter. The 16-bit counter starts down-counting when a value different than zero is loaded. An interrupt is generated when the counter is null. The capture module is a frame analyzer. It stores the period of time between two edges of a signal in a register. This period is described as a number of counter cycles. The capture allows data transfers with the PDC. The AT91SAM7A2 includes four PWM channels. Each channel can generate pulses. The frequency and the duty cycle of each channel can be configured. The watch timer provides a seconds counter and an alarm function. The alarm register has a resolution of 30.5 s. This allows a 32-bit register to have sufficient range to cater for a 24 or 36 hour period. The AT91SAM7A2 has an internal watchdog which can be used to prevent system lock-up if the software becomes trapped in a deadlock. The AT91SAM7A2 provides registers which implement the following special functions. * * Chip Identification RESET Status
CAPT: Capture Module PWM: Pulse Width Modulation WT: Watch Timer
WD: Watch Dog SFM: Special Function Module
PRELIMINARY
6021BS-ATARM-06-Jul-04
9
PRELIMINARY
ADC: Analog to Digital Converter
The two identical 8-channel 10-bit Analog-to-Digital Converters (ADC) are based on a Successive Approximation Register (SAR) approach. Each ADC has 8 analog input pins, ANA0IN0 to ANA0IN7 and ANA1IN0 to ANA1IN7, and provides an interrupt signal to the AIC. Both ADCs share the analog power supply pins VDDA and GNDA, and the input reference voltage pin VREFP. Each channel can be enabled or disabled independently, and has its own data register. The ADC can be configured to automatically enter Sleep Mode after a conversion sequence, and can be triggered by the software. The ADC allows a data transfer with the PDC. The AT91SAM7A2 Power Management Controller allows optimization of power consumption. The PMC enables/disables the clock inputs of the PDC and ARM core. Moreover, the main oscillator, the PLL and the analog peripherals can be put in standby mode allowing minimum power consumption to be obtained. The PMC provides the following operating modes: * * * Normal: the clock generator provides clock to chip. Wait Mode: the ARM core clock is deactivated. Slow Mode: the clock generator is deactivated, the system is clocked at 32.768 kHz.
PMC: Power Management Controller
Each peripheral clock can be independently stopped or started directly in the peripheral to further reduce power consumption in Normal, Wait and Slow Modes.
ICE Debug Mode
ARM Standard Embedded In Circuit Emulation is supported via the ICE port. It is connected to a host computer via an external ICE Interface. In ICE Debug Mode the ARM core responds with a non-JTAG chip ID which identifies the core to the ICE system. This is not JTAG IEEE 1149.1 compliant.
10
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
AT91SAM7A2 - Summary
Ordering Information
Table 3. Ordering Information
Ordering Code AT91SAM7A2-AI Package TQFP 176 Temperature Operating Range Industrial (-40C to +85C)
PRELIMINARY
6021BS-ATARM-06-Jul-04
11
PRELIMINARY
Packaging Information
Package Drawing
Figure 3. 176-lead LQFP Package Drawing
aaa
bbb
PIN 1
2 S
ccc
3
ddd
R1
R2 0.25
c
c1
1 L1
12
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
AT91SAM7A2 - Summary
Table 4. Package Dimensions (mm)
Symbol c c1 L L1 R2 R1 S q 1 2 3 A A1 A2 0.05 1.35 1.4 0.08 0.08 0.2 0 0 11 11 12 12 13 13 1.6 0.15 1.45 3.5 7 Min 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.20 0.16 0.75
Tolerances of Form and Position aaa bbb 0.2 0.2
Table 5. Lead Count Dimensions (mm)
Pin Count 176 D/E BSC 26.0 D1/E1 BSC 24.0 b Min 0.17 Nom 0.20 Max 0.27 Min 0.17 b1 Nom 0.20 Max 0.23 e BSC 0.50
ccc 0.10
ddd 0.08
Table 6. Device and 176-lead LQFP Package Maximum Weight
1900 mg
PRELIMINARY
6021BS-ATARM-06-Jul-04
13
PRELIMINARY
Soldering Profile
Table 7 gives the recommended soldering profile from J-STD-20. Table 7. Soldering Profile
Convection or IR/Convection Average Ramp-up Rate (183C to Peak) Preheat Temperature 125C 25C Temperature Maintained Above 183C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature 3C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0C or 235 +5/-0C 6C/sec. 6 min. max 60 sec. 215 to 219C or 235 +5/-0C 10C/sec. VPR 10C/sec.
Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235C, not 220C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 8 below. Table 8. Recommended Package Reflow Conditions (1, 2, 3)
Parameter Convection VPR IR/Convection Notes: Temperature 220 +5/-0C 215 to 219C 220 +5/-0C
1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220C (unless 235C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability.
A maximum of three reflow passes is allowed per component.
14
AT91SAM7A2 - Summary
6021BS-ATARM-06-Jul-04
AT91SAM7A2 - Summary
Document Details
Title Literature Number AT91SAM7A2 - Summary 6021S
Revision History
Version AS Version BS Publication Date: 30-Mar-04 Publication Date: 06-Jul-04
Revisions Since Previous Version Page: all Page: 2 Status changed to Preliminary Block Diagram modified
PRELIMINARY
6021BS-ATARM-06-Jul-04
15
PRELIMINARY
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
(c) Atmel Corporation 2004. All rights reserved. Atmel (R) and combinations thereof, are the registered trademarks of Atmel Corporation or its subsidiaries. ARM (R), ARM7TDMI(R), ARM (R)Thumb (R) and ARM Powered(R) are the registered trademarks and AMBATM is the trademark of ARM Ltd. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
6021BS-ATARM-06-Jul-04 0M

▲Up To Search▲

Price & Availability of AT91SAM7A20407

	To Download AT91SAM7A20407 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .